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w wm8785 24-bit, 192khz stereo adc wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, december 2006, rev 4.1 copyright ? 2006 wolfson microelectronics plc description the wm8785 is a stereo audio adc with differential inputs designed for high performance recordable media applications. data is provided as a pcm output. stereo 24-bit multi-bit sigma-delta adcs are used with digital audio output word lengths of 16 to 32 bits, and sampling rates from 8khz to 192khz. the device has a selectable high pass filter to remove residual dc offsets. the device also supports a tdm bus for data out. the device is controlled via a 2 or 3 wire serial interface. the interface provides access to all features including oversampling rate, audio format, powerdown, master/slave control and digital signal manipulation. the device is supplied in a 20-lead ssop package. features ? snr 111db (?a? weighted @ 48khz) ? thd -102db (at -0.1db) ? sampling frequency: 8 ? 192khz ? 2 or 3 wire microprocessor control interface ? master or slave clocking mode ? programmable audio data interface modes - i 2 s, left, right justified or dsp - 16/20/24/32 bit word lengths ? a tdm bus is supported for data out ? supply voltages - analogue 4.5 to 5.5v - digital core: 2.7v to 3.6v ? 20-lead ssop package applications ? recordable dvd players ? personal video recorders ? high end sound cards ? studio audio processing equipment block diagram
wm8785 production data w pd rev 4.1 december 2006 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................5 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 terminology ............................................................................................................ 7 signal timing requirements .......................................................................8 system clock timing ............................................................................................. 8 audio interface timing ? master mode, pcm data ...................................... 8 audio interface timing ? slave mode, pcm data ......................................... 9 control interface timing ? 3-wire mode ...................................................... 9 control interface timing ? 2-wire mode .................................................... 10 power-on reset ................................................................................................... 11 digital filter characteristics ...............................................................12 terminology .......................................................................................................... 12 filter responses ..........................................................................................13 device description .......................................................................................16 introduction ......................................................................................................... 16 digital audio interface ..................................................................................... 16 digital high pass .................................................................................................. 20 data out pin disable ........................................................................................... 21 control interface.............................................................................................. 21 time division multiplexed data out............................................................... 22 tdm selection ....................................................................................................... 23 oversampling ratios and sigma-delta modulator frequency.......... 26 master clock and audio sample rates........................................................ 26 mlck and lrclk phase relationship.............................................................. 27 power down control ........................................................................................ 27 register map ......................................................................................................... 28 applications information .........................................................................29 recommended external components .......................................................... 29 package dimensions ....................................................................................30 important notice ..........................................................................................31 address: .................................................................................................................. 31
production data wm8785 w pd rev 4.1 december 2006 3 pin configuration 1 2 3 4 5 6 7 8 vmid csb nc dvdd dgnd ainr- ainr+ ainl- vref lrclk nc agnd avdd ainl+ vrefgnd dout 13 14 15 16 17 20 19 18 9 10 bclk mclk sclk sdin 11 12 ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8785geds/v -25 c to +85 c 20-lead ssop (pb-free) msl3 260 o c wm8785geds/rv -25 c to +85 c 20-lead ssop (pb-free, tape and reel) msl3 260 o c note: reel quantity = 2,000
wm8785 production data w pd rev 4.1 december 2006 4 pin description pin name type description 1 ainl+ analogue input left channel positive input 2 ainl- analogue input left channel negative input 3 vrefgnd analogue reference negative reference connection 4 avdd supply analogue supply 5 agnd supply analogue ground (return path for avdd) 6 lrclk digital input / output audio interface left / right clock 7 dout digital output adc digital audio data 8 bclk digital input / output audio interface bit clock 9 mclk digital input master clock 10 nc nc no connection 11 sclk digital input control interface clock input / 2 wire output 12 sdin digital input / output control interface data input 13 csb digital input chip select / control interface format selection / 3 wire address select 14 nc nc no connection 15 dvdd supply digital supply 16 dgnd supply digital ground (return path for dvdd) 17 vmid analogue output midrail voltage decoupling capacitor 18 vref analogue reference reference voltage decoupling capacitor 19 ainr- analogue input right channel negative input 20 ainr+ analogue input right channel positive input
production data wm8785 w pd rev 4.1 december 2006 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max digital supply voltage -0.3v +3.63v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd + 0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 40mhz operating temperature range, t a -25 c +85 c storage temperature after soldering -65 c +150 c note: analogue and digital grounds must always be within 0.3v of each other. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd 2.7 3.6 v analogue supply range avdd 4.5 5.5 v ground dgnd,agnd 0 v
wm8785 production data w pd rev 4.1 december 2006 6 electrical characteristics test conditions dvdd = 3.3v, avdd = 5.0v, t a = +25 o c, 1khz signal, a-weighted, fs = 48khz, mclk = 256fs, 24-bit audio data, slave mode unless otherwise stated. parameter symbol test conditions min typ max unit adc performance full scale input signal level (for adc 0db input) 2.0 v rms input resistance 10 k ? input capacitance 10 pf a-weighted, @ fs = 48khz 102 111 db signal to noise ratio (note 1,2,4) snr unweighted, @ fs = 48khz 108 db a-weighted, @ fs = 96khz 111 db signal to noise ratio (note 1,2,4) snr unweighted, @ fs = 96khz 108 db a-weighted, @ fs = 192khz 111 db signal to noise ratio (note 1,2,4) snr unweighted, @ fs = 192khz 108 db 1khz, -0.1db full scale @ fs = 48khz -102 -92 db 1khz, -0.1db full scale @ fs = 96khz -102 db total harmonic distortion thd 1khz, -0.1db full scale @ fs = 192khz -102 db total harmonic distortion thd 1khz, -0.1db full scale @ fs = 48khz 0.0008 0.0025 % 1khz, -0.1db full scale @ fs = 96khz 0.0008 % 1khz, -0.1db full scale @ fs = 192khz 0.0008 % dynamic range dnr -60dbfs 102 111 db channel level matching 20khz signal 0.1 db 1 khz 100mvpp, applied to avdd, dvdd 50 db power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db digital logic levels (cmos levels) input low level v il 0.3 x dvdd v input high level v ih 0.7 x dvdd v input leakage current -1 0.2 +1 a input capacitance 5 pf output low v ol i ol =1ma 0.1 x dvdd v output high v oh i oh = -1ma 0.9 x dvdd v analogue reference levels midrail reference voltage vmid avdd to vmid and vmid to vrefgnd ?3% avdd/2 +3% v potential divider resistance r vmid avdd to vmid and vmid to gnd 50 k ? buffered reference voltage vref ?3% 0.8 x avdd +3% v
production data wm8785 w pd rev 4.1 december 2006 7 test conditions dvdd = 3.3v, avdd = 5.0v, t a = +25 o c, 1khz signal, a-weighted, fs = 48khz, mclk = 256fs, 24-bit audio data, slave mode unless otherwise stated. parameter symbol test conditions min typ max unit supply current analogue supply current 27 ma digital supply current 5 ma power down 22 ua note: 1. vmid is decoupled with 10uf and 0.1uf capacitors close to the device package. smaller capacitors may reduce performance. terminology 1. signal-to-noise ratio (db) ? ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, over a 20hz to 20khz bandwidth. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 5. all performance measurements are done with a 20khz low pass filter, and where noted an a-weight filter, except where noted. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although this is not audible, it may affect dynamic specification values
wm8785 production data w pd rev 4.1 december 2006 8 signal timing requirements system clock timing figure 1 system clock timing requirements test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock cycle time t mclky 25 ns mclk duty cycle t mclkds 60:40 40:60 audio interface timing ? master mode, pcm data figure 2 digital audio data timing ? master mode (see control interface) test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, master mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information lrclk propagation delay from bclk falling edge t dl 0 10 ns dout propagation delay from bclk falling edge t dda 0 11 ns
production data wm8785 w pd rev 4.1 december 2006 9 audio interface timing ? slave mode, pcm data figure 3 digital audio data timing ? slave mode test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 25 ns lrclk set-up time to bclk rising edge t lrsu 10 ns lrclk hold time from bclk rising edge t lrh 10 ns dout propagation delay from bclk falling edge t dd 0 11 ns control interface timing ? 3-wire mode csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 4 control interface timing ? 3-wire serial control mode test conditions dvdd = 3.3v, dvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 4 6 ns
wm8785 production data w pd rev 4.1 december 2006 10 control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 5 control interface timing ? 2-wire serial control mode test conditions dvdd = 3.3v, dvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 5 mhz sclk low pulse-width t 1 80 ns sclk high pulse-width t 2 80 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 4 6 ns
production data wm8785 w pd rev 4.1 december 2006 11 power-on reset the wm8785 has an internal power-on reset circuit. the reset sequence is entered at power-on or power-up (dvdd). until the internal reset is removed, dout is forced to zero. dout remains zero for a count equal to 32 sample clocks, after power up. (this count is driven by mclk and is independent of any external lrclk). figure 6 por circuit figure 7 por timing
wm8785 production data w pd rev 4.1 december 2006 12 digital filter characteristics the wm8785 digital filter characteristics scale with sample rate. parameter test conditions min typ max unit adc sample rate (single rate ? 48khz typically) +/- 0.005db 0 0.454fs passband -6db 0.5fs passband ripple +/- 0.005 db stopband 0.546fs stopband attenuation f > 0.546fs -85 db group delay 32/fs s adc sample rate (dual rate - 96khz typically) +/- 0.005db 0 0.454fs passband -6db 0.5fs passband ripple +/- 0.005 db stopband 0.546fs stopband attenuation f > 0.546fs -85 db group delay 32/fs s adc sample rate (quad rate - 192khz typically) +/- 0.005db 0 0.25fs -3db 0.45fs passband -6db 0.5fs passband ripple +/- 0.005 db stopband 0.75fs stopband attenuation f > 0.75fs -85 db group delay 10/fs s -3db 3.7 -0.5db 10.4 high pass filter corner frequency -0.1db 21.6 hz terminology 1. stop band attenuation (db) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region
production data wm8785 w pd rev 4.1 december 2006 13 filter responses single rate 48k -100 -80 -60 -40 -20 0 00.511.522.533.54 frequency (fs) response (db) figure 8 single rate 48k filter response -100 -80 -60 -40 -20 0 0.40.450.50.550.6 frequency (fs) response (db) figure 9 single rate 48k filter response -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 10 single rate 48k filter response
wm8785 production data w pd rev 4.1 december 2006 14 dual rate 96k -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 frequency (fs) response (db) figure 11 dual rate 96k filter response -100 -80 -60 -40 -20 0 0.4 0.45 0.5 0.55 0.6 frequency (fs) response (db) figure 12 dual rate 96k filter response -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 13 dual rate 96k filter response
production data wm8785 w pd rev 4.1 december 2006 15 quad rate 192k -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 frequency (fs) response (db) figure 14 quad rate 192k filter response -100 -80 -60 -40 -20 0 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (fs) response (db) figure 15 quad rate 192k filter response -3.5 -3.4 -3.3 -3.2 -3.1 -3 -2.9 -2.8 -2.7 -2.6 -2.5 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 16 quad rate 192k filter response
wm8785 production data w pd rev 4.1 december 2006 16 device description introduction the wm8785 is a high performance stereo audio adc designed for demanding recording applications such as dvd recorders, studio mixers, pvrs, and av amplifiers. the wm8785 consists of stereo line level inputs, followed by a sigma-delta modulator and digital filtering. the wm8785 uses a multi-bit high-order oversampling architecture delivering high snr operating at oversampling ratios from 128fs to 32fs according to the sample rate. sample rates from 8khz to 192khz are supported. the wm8785 supports master clock rates from 128fs to 768fs. the digital filter is a high performance linear phase fir filter. the digital filters are optimised for each sample rate. also included is a selectable high pass filter to remove residual dc offsets from the input signal. the output from the adc is available on a configurable digital audio interface. it supports a number of audio data formats including i 2 s, left justified and right justified or dsp, and can operate in master or slave modes. the wm8785 can be controlled through a 2 wire or 3 wire mpu control interface. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. a tdm bus is supported for multiplexing data output. the wm8785 can be powered down under software control to reduce system power consumption. digital audio interface the digital audio interface uses three pins: ? dout: adc data output ? lrclk: adc data alignment clock ? bclk: bit clock, for synchronisation the digital audio interface takes the data from the internal adc digital filters and places it on dout and lrclk. dout is the formatted digital audio data stream output from the adc digital filters with left and right channels multiplexed together. lrclk is an alignment clock that controls whether left or right channel data is present on the dout line. dout and lrclk are synchronous with the bclk signal with each data bit transition signified by a bclk high to low transition. dout is always an output. bclk and lrclk maybe inputs or outputs depending whether the device is in master or slave mode, (see master and slave mode operation, below). four different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the wm8785 can be configured as either a master or slave mode device. as a master device the wm8785 generates bclk and lrclk and thus controls sequencing of the data transfer on dout. in slave mode, the wm8785 responds with data to clocks it receives over the digital audio interface. the mode can be selected by setting mcr=000 (see table below). master and slave modes are illustrated below. figure 17a master mode figure 17b slave mode
production data wm8785 w pd rev 4.1 december 2006 17 audio data formats in left justified mode, the msb is available on the first rising edge of bclk following an lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 18 left justified audio interface (assuming n-bit word length) in right justified mode, the lsb is available on the last rising edge of bclk before an lrclk transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrclk transition. figure 19 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following an lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 20 i 2 s justified audio interface (assuming n-bit word length)
wm8785 production data w pd rev 4.1 december 2006 18 in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 21 and figure 22. in device slave mode, figure 23 and figure 24, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 21 dsp/pcm mode audio interface (mode a, lrp=0, master) figure 22 dsp/pcm mode audio interface (mode b, lrp=1, master)
production data wm8785 w pd rev 4.1 december 2006 19 figure 23 dsp/pcm mode audio interface (mode a, lrp=0, slave) figure 24 dsp/pcm mode audio interface (mode b, lrp=1, slave) audio interface control the register bits controlling the audio interface are summarised below. note that dynamically changing the software format may cause erroneous operation of the interfaces and is therefore not recommended. all adc data is 2?s complement. the length of the digital audio data is programmable at 16/20/24 or 32 bits, as shown below. the adc digital filters process data using 24 bits. if the wm8785 is programmed to output 16 or 20 bit data then it strips the lsbs from the 24 bit data. if the device is programmed to output 32 bits then it packs the lsbs with zeros. in master mode lrclk and bclk are generated on chip. in slave mode they are received from an external source.
wm8785 production data w pd rev 4.1 december 2006 20 register address bit label default description r0 (00h) sample rate and digital audio interface format 6:5 format 10 audio data format select 11: dsp format 10: i 2 s format 01: left justified 00: right justified 1:0 wl 10 audio data word length 11: 32 bits (see note) 10: 24 bits 01: 20 bits 00: 16 bits right, left and i 2 s modes ? lrclk polarity 1 = invert lrclk polarity 0 = normal lrclk polarity 2 lrp 0 dsp mode ? a/b select 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 3 bclkinv 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted r1 (01h) digital audio interface format and tdm 4 lrswap 0 left/right channel swap 1 = swap left and right dac data in audio interface 0 = output left and right data as normal table 1 audio data format control note: right justified mode does not support 32-bit data. if wl=11 in right justified mode, the actual word length is 24 bits. digital high pass the high pass filter can be enabled using the hpfl and hpfr bits (see digital filter characteristics) register address bit label default description 0 hpfr 1 digital high pass filter, right channel 0 = hpf off 1 = hpf on r2(02h) hpfilter , output disable, power down, mono mode 1 hpfl 1 digital high pass filter, left channel 0 = hpf off 1 = hpf on table 2 oversampling ratio selection the high pass filter should only be disabled for procedures such as dc offset calibration. it should be noted that the output range of the adc with a dc level applied and hpf disabled is as follows: maximum code: 7fdfb0 minimum code: 802033
production data wm8785 w pd rev 4.1 december 2006 21 data out pin disable to prevent any communication problems on the audio interface, the interface can be disabled (dout tristated and floating) using the sdodis bit. register address bit label default description r2(02h) hp filter , output disable, power down, mono mode 2 sdodis 0 dout serial data pin disable 0 = dout pin enabled 1 = dout pin off (high impedance) table 3 oversampling ratio selection control interface selection of control mode the wm8785 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are register bits, corresponding to the 9 bits in each control register. the control interface can operate as either a 3-wire or 2-wire mpu interface. the csb pin is sampled at power-up and selects the interface format. after power-up the pin is available to latch in control data in 3-wire interface mode. figure 25 control interface mode selection csb pin status interface format low 2 wire high 3 wire table 4 control interface mode selection setup/hold time tpusetup 250us tpuhold 250us table 5 control interface mode selection
wm8785 production data w pd rev 4.1 december 2006 22 3-wire serial control mode in 3-wire mode, every rising edge of sclk clo cks in one data bit from the sdin pin. a rising edge on csb latches in a complete control word consisting of the last 16 bits. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sdin sclk csb control register address control register data bits latch figure 26 3-wire serial control interface 2-wire serial control mode the wm8785 supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the wm8785). the wm8785 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8785 and the r/w bit is ?0?, indicating a write, then the wm8785 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1?, the wm8785 returns to the idle condition and wait for a new start condition and valid address. once the wm8785 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8785 register address plus the first bit of register data). the wm8785 then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8785 acknowledges again by pulling sdin low. the transfer of data is complete when there is a low to high transition on sdin while sclk is high. after receiving a complete address and data sequence the wm8785 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 1 (bits 15 to 8) remaining 8 bits of register data stop start ack (low) ack (low) figure 27 2-wire serial control interface the wm8785 device address is 0011010. time division multiplexed data out the wm8785 can be used to time division multiplex several data channels at once. for example, the diagram below illustrates 4 devices connected to the same tdm bus. while one dout pin is driving data, the others will be tri-stated.
production data wm8785 w pd rev 4.1 december 2006 23 figure 28 wm8785 in time division multiplexing setup note: 1. tdm is only available in slave mode. 2. right justified mode is not supported tdm selection the figure below indicates how data is multiplexed onto the tdm bus, in left justified mode. this assumes we have 4 devices, and each device has 2 data channels: ? lchan = left channel ? rchan = right channel each channel is allocated 32 bclks
wm8785 production data w pd rev 4.1 december 2006 24 figure 29 wm8785 in time division multiplexing left justified mode up to 4 devices (8 channels) can be supported, which would require 256 bclks per sample. (whereas 128 bclks will allow only 2 devices, or 4 channels). the table below shows the range of bclk frequencies required. bclk rate devices that can be supported over-sample ratios supported (set by osr) 64 fs 128 fs 192 fs 1 1, 2 1, 2 single/dual/quad rates all supported 256 fs 1, 2, 3, 4 single rate only supported table 6 range of bclk frequencies required note: mclk frequency must always be greater or equal to bclk frequency to avoid bus contention all chips on the tdm should be programmed before dout is released after power up (dout is held at vss for 32 samples after power-up). alternatively sdodis should be set while devices are programmed (to tri-state dout).
production data wm8785 w pd rev 4.1 december 2006 25 two registers must be set to enter tdm mode: ? devno[2:0] sets the number of devices which are on the bus ? tdm[2:0] allocates a tdm slot to the device register address bit label default description r1(h01) clocking, sample rates, oversampling and signal control 7:5 devno[2:0] 000 number of tdm devices 000 = 1 device 001 = 2 devices 010 = 3 devices 011 = 4 devices table 7 devno register address bit label default description r2(h02) clocking, sample rates, oversampling and signal control 8:6 tdm[2:0] 000 time division multiplexing device select 000 = device 0 (no delay) 001 = device 1 (64 bclk delay) 010 = device 2 (128 bclk delay) 011 = device 3 (192 bclk delay) table 8 tdm note: when tdm is not required, the register will default to 000 (normal operation) the figures below indicate tdm mode for i2s and dsp mode a. figure 30 tdm bus i 2 s mode
wm8785 production data w pd rev 4.1 december 2006 26 oversampling ratios and sigma-delta modulator frequency for correct operation of the device and optimal performance, the user must select the appropriate adc modulator oversampling ratio. the oversampling ratio is selected using the osr[1:0] bits. register address bit label default description r0(h00) signal control 4:3 osr[1:0] 00 oversampling ratio control 00: single rate (128fs) 01: dual rate (64fs) 10: quad rate (32fs) 11: not valid table 9 oversampling ratio selection the wm8785 can operate at sample rates from 8khz to 192khz. the wm8785 uses a sigma-delta modulator that operates at frequencies between 1.024mhz and 6.144mhz sampling rate (lrclk) oversampling ratio sigma-delta modulator frequency (mhz) 8khz single rate (128fs) 1.024 32khz single rate (128fs) 4.096 44.1khz single rate (128fs) 5.6448 48khz single rate (128fs) 6.144 96khz dual rate (64fs) 6.144 192khz quad rate (32fs) 6.144 table 10 sigma-delta modulator frequency master clock and audio sample rates master clock frequencies of 128f s , 192f s , 256f s , 384f s , 512f s and 768f s are supported. in slave mode the wm8785 automatically detects the audio sample rate. in master mode the master clock frequency is selected using mcr[2:0] bits. this is described in table below. register address bit label default description r0(h00) clocking, sample rates, 2:0 mcr[2:0] 000 master/slave selection 000: slave mode 001: master mode, 128fs 010: master mode, 192fs 011: master mode, 256fs 100: master mode, 384fs 101: master mode, 512fs 110: master mode, 768fs table 11 master clock frequency the master clock (mclk) is used to operate the digital filters and the noise shaping circuits. the wm8785 supports a wide range of master clock frequencies, and can generate many commonly used audio sample rates directly from the master clock. table 1 shows the recommended master clock frequencies for different sample rates
production data wm8785 w pd rev 4.1 december 2006 27 master clock frequency (mhz) sampling rate (lrclk) oversampling ratio 128fs 192fs 256fs 384fs 512fs 768fs 32khz single rate - - 8.192 12.288 16.384 24.576 44.1khz single rate - - 11.2896 16.9344 22.5792 33.8688 48khz single rate - - 12.288 18.432 24.576 36.864 96khz dual rate - - 24.576 36.864 - - 192khz quad rate 24.576 36.864 - - - - table 12 slave mode: recommended master clock frequency selection mlck and lrclk phase relationship the wm8785 does not require a specific phase relationship between mlck and lrclk. if the relationship between mclk and lrclk changes by more than +/-8 bclks in a 64 blck frame, the wm8785 will attempt to re-synchronise. during re-synchronisation, data samples may be dropped or duplicated. power down control the wm8785 can be powered down by setting the pwrdnl and pwrdnr bits. this is described in the table below. register address bit label default description 3 pwrdnr 0 power down right channel 0 = power on 1 = power off r2(02h) signal control 4 pwrdnl 0 power down left channel 0 = power on 1 = power off table 13 power down control
wm8785 production data w pd rev 4.1 december 2006 28 register map register address remark bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 default r0(00h) 00_0000 sample rate and audio if format 0 0 format osr mcr 0_0000_0011 r1(01h) 00_0001 audio if format and tdm 0 devno lrswp bclkinv lrp wl 0_0000_1010 r2(02h) 00_0010 signal control t d m 0 pwrdnl pwrdnr sdodis hpfl hpfr 0_0000_0011 r7(07h) 00_0111 reset writing to reg 7 will cause software reset 0_0000_0000 table 14 register map for control interface notes: 1. all unused register bits should be set to zero 2. the interface will initiate swrb whenever r7 is addressed, regardless of the data input. 3. swrb is released on the next register write or after 4 mclk cycles (which ever occurs first). 4. until the swrb is released, dout is forced to zero. 5. dout remains zero for a count of 32 sample clocks swrb is released, this count is driven by mclk and is independent of any external lrclk.
production data wm8785 w pd rev 4.1 december 2006 29 applications information recommended external components notes: 1. agnd and dgnd should be connected as close to the wm8785 as possible. 2. c1 to c6 should be placed as close to the wm8785 device as possible. 3. capacitor types should be chosen carefully. capacitors with very low esr are recommended for optimum performance, such as x7 r. vmid and vref decoupling capacitors must be high quality electrolytic capacitors to achieve datasheet performance; ceramic capacitors are not acceptable . 4. an active input filter is required to achieve datasheet performance. the circuit shown is a tested inverting reference examp le. figure 31 external component diagram
wm8785 production data w pd rev 4.1 december 2006 30 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.c ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 ref: a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e - jedec.95, mo 150 0 o 4 o 8 o e 1 l 1 1.25 ref c l gauge plane 0.25 l 1
production data wm8785 w pd rev 4.1 december 2006 31 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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